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Pat. 11101792 United States, Int. Cl.22 H03K 17/16, H02M 1/08, H02M 7/00, H02M 7/537, H02M 1/00. Circuitry and methodology benefiting from reduced gate loss : Appl. N 16/847397 : Filed 13.04.2020 : Pub. 24.08.2021 : / Juan Rivas-Davila, Jiale Xu, Lei Gu ; Assignee Leland Stanford Junior University ; NN p. : patents.google.com : URL: https://patents.google.com/patent/US11101792/en?oq=US11101792.html (дата обращения: ДД.ММ.ГГГГ).